phase shifter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_reg is
Port ( CLK : in STD_LOGIC;
RES : in STD_LOGIC;
SER_IN : in STD_LOGIC;
PAR_OUT : out STD_LOGIC_VECTOR (9 downto 0));
end shift_reg;

architecture Behavioral of shift_reg is

signal temp_reg : std_logic_vector(9 downto 0);

begin


process (CLK)
begin
if RES = '0' then
temp_reg <= (others => '0');
elsif rising_edge(CLK) then
for i in 0 to 8 loop
temp_reg(i+1) <= temp_reg(i);
end loop;
temp_reg(0) <= SER_IN;
end if;
end process;

PAR_OUT <= temp_reg;

end Behavioral;